`timescale 1ns/1ns

`define PRINTF_COND 0

module tb_top;

reg      clk;        // Clock
reg      rst;        // Reset

    wire    [7:0] sink_data;
    wire          sink_ready;
    wire          sink_valid;
    wire    [7:0] source_data;
    wire          source_ready;
    wire          source_valid;

sim simDUT0 (
    .serial_sink_data    ( 8'b0    ),
    .serial_sink_ready   ( sink_ready   ),
    .serial_sink_valid   ( 1'b0   ),
    .serial_source_data  ( source_data  ),
    .serial_source_ready ( 1'b1 ),
    .serial_source_valid ( source_valid ),
    .sim_trace           (              ),
    .sys_clk             ( clk          )
);


always @ (negedge clk) begin

    if (source_valid) begin
       $write("%c", source_data); 
       //$display("%c", source_data); 
    end

end


initial begin

    $display;
    $display("\n ######################################################### \n");
    $display;

`ifdef WAVES
    $dumpfile("wave.vcd");
    $dumpvars(3, tb_top);
    $display("INFO: Signal dump enabled ...\n\n");
`endif

    clk = 0;

    rst = 1;
    force simDUT0.int_rst = 1'b1;
    repeat(5)   @(posedge clk);
    rst = 0;
    force simDUT0.int_rst = 1'b0;
    repeat(20000000)  @(posedge clk);
    $finish;
 end

always #5 clk = !clk;

endmodule
